PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F45J50-I/SOSQTP
Microchip Technology
PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
FIGURE 30-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
83
71
72
SCKx
(CKP = 1)
80
SDOx
MSb
bit 6 - - - - - - 1
SDIx
Note:
75, 76
MSb In
74
73
Refer to Figure 30-4 for load conditions.
bit 6 - - - - 1
LSb
77
LSb In
TABLE 30-23: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
3 TCY
—
70A TSSL2WB SSx to Write to SSPxBUF
3 TCY
—
71
TSCH
71A
SCKx Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 —
Single byte
40
—
72
TSCL
72A
SCKx Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 —
Single byte
40
—
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
25
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of 1.5 TCY + 40 —
Byte 2
74
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
35
—
100
—
75
TDOR
SDOx Data Output Rise Time
—
25
76
TDOF
SDOx Data Output Fall Time
—
25
77
TSSH2DOZ SSx to SDOx Output High-Impedance
10
70
80
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
—
50
—
100
83
TSCH2SSH, SSx after SCKx Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns VDD = 3.3V,
VDDCORE = 2.5V
ns VDD = 2.15V
ns PORTB or PORTC
ns PORTB or PORTC
ns
ns VDD = 3.3V,
VDDCORE = 2.5V
ns VDD = 2.15V
ns
DS39931D-page 522
2011 Microchip Technology Inc.
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