PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F45J50-I/SOSQTP
Microchip Technology
PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
FIGURE 30-16:
SSx
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCKx
(CKP = 0)
71
72
73
SCKx
(CKP = 1)
80
SDOx
MSb
bit 6 - - - - - - 1
SDIx
MSb In
75, 76
bit 6 - - - - 1
74
Note: Refer to Figure 30-4 for load conditions.
LSb
LSb In
83
77
TABLE 30-24: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
3 TCY
—
70A TSSL2WB SSx to Write to SSPxBUF
3 TCY
—
71
TSCH
71A
SCKx Input High Time
(Slave mode)
Continuous
Single byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCKx Input Low Time
(Slave mode)
Continuous
Single byte
1.25 TCY + 30 —
40
—
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
25
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
35
—
100
—
75
TDOR
SDOx Data Output Rise Time
—
25
76
TDOF
SDOx Data Output Fall Time
—
25
77
TSSH2DOZ SSx to SDOx Output High-Impedance
10
70
80
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
—
50
—
100
81
TDOV2SCH, SDOx Data Output Setup to SCKx Edge
TDOV2SCL
TCY
—
82
TSSL2DOV SDOx Data Output Valid after SSx Edge
—
50
83
TSCH2SSH, SSx after SCKx Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns VDD = 3.3V,
VDDCORE = 2.5V
ns VDD = 2.15V
ns
ns
ns
ns VDD = 3.3V,
VDDCORE = 2.5V
ns VDD = 2.15V
ns
ns
ns
2011 Microchip Technology Inc.
DS39931D-page 523
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