PIC18F6310/6410/8310/8410
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
INDF2
6X10 8X10
N/A
N/A
N/A
POSTINC2
6X10 8X10
N/A
N/A
N/A
POSTDEC2
6X10 8X10
N/A
N/A
N/A
PREINC2
6X10 8X10
N/A
N/A
N/A
PLUSW2
6X10 8X10
N/A
N/A
N/A
FSR2H
6X10 8X10
---- xxxx
---- uuuu
---- uuuu
FSR2L
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
6X10 8X10
---x xxxx
---u uuuu
---u uuuu
TMR0H
6X10 8X10
0000 0000
0000 0000
uuuu uuuu
TMR0L
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
6X10 8X10
1111 1111
1111 1111
uuuu uuuu
OSCCON
6X10 8X10
0100 q000
0100 00q0
uuuu uuqu
HLVDCON
6X10 8X10
--00 0101
--00 0101
--uu uuuu
WDTCON
RCON(4)
6X10 8X10
6X10 8X10
---- ---0
0q-1 11q0
---- ---0
0q-q qquu
---- ---u
uq-u qquu
TMR1H
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
6X10 8X10
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
6X10 8X10
0000 0000
0000 0000
uuuu uuuu
PR2
6X10 8X10
1111 1111
1111 1111
1111 1111
T2CON
6X10 8X10
-000 0000
-000 0000
-uuu uuuu
SSPBUF
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
6X10 8X10
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
6X10 8X10
0000 0000
0000 0000
uuuu uuuu
SSPCON1
6X10 8X10
0000 0000
0000 0000
uuuu uuuu
SSPCON2
6X10 8X10
0000 0000
0000 0000
uuuu uuuu
ADRESH
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
6X10 8X10
--00 0000
--00 0000
--uu uuuu
ADCON1
6X10 8X10
--00 0000
--00 0000
--uu uuuu
ADCON2
6X10 8X10
0-00 0000
0-00 0000
u-uu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
DS39635A-page 58
Preliminary
2004 Microchip Technology Inc.