PIC18F258-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F258-I/SP

28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

Microchip Technology 

PIC18FXX8

CLRF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

Clear f

[ label ] CLRF f [,a]

0 ≤ f ≤ 255

a ∈ [0,1]

000h → f

1→Z

Z

0110 101a ffff ffff

Clears the contents of the specified

register. If ‘a’ is ‘0’, the Access Bank will

be selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be selected

as per the BSR value (default).

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write

register ‘f’

Example:

CLRF

Before Instruction

FLAG_REG =

After Instruction

FLAG_REG =

FLAG_REG

0x5A

0x00

CLRWDT

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

Clear Watchdog Timer

[ label ] CLRWDT

None

000h → WDT,

000h → WDT postscaler,

1 → TO,

1 → PD

TO, PD

0000 0000 0000 0100

CLRWDT instruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits TO

and PD are set.

1

1

Q2

No

operation

Q3

Process

Data

Q4

No

operation

Example:

CLRWDT

Before Instruction

WDT Counter

=

After Instruction

WDT Counter

=

WDT Postscaler =

TO

=

PD

=

?

0x00

0

1

1

© 2006 Microchip Technology Inc.

DS41159E-page 297

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