ST92P141K4D0 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92P141K4D0 Datasheet PDF : 179 Pages
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ST92141 - ELECTRICAL CHARACTERISTICS
SPI TIMING TABLE
(VDD = 5V ± 10%, TA = –40°C to +85°C, CLoad = 50pF, fINTCLK = 25MHz, unless otherwise specified)
N° Symbol
Parameter
Condition
Value(1)
Min
Max
Unit
fSPI SPI frequency
1 tSPI SPI clock period
Master
Slave
Master
Slave
fINTCLK / 128
0
4 x Tck
2 x Tck
fINTCLK / 4
fINTCLK / 2
2 tLead Enable lead time
Slave
40
3 tLag Enable lag time
Slave
40
4 tSPI_H Clock (SCK) high time
Master
Slave
80
90
5 tSPI_L Clock (SCK) low time
Master
Slave
80
90
6 tSU Data set-up time
Master
Slave
40
40
7
tH Data hold time (inputs)
Master
Slave
40
40
8
tA
Access time (time to data active
from high impedance state)
Slave
9
tDis
Disable time (hold time to high im-
pedance state)
0
120
240
10 tV Data valid
Master (before capture edge) Tck / 4
Slave (after enable edge)
120
11 tHold Data hold time (outputs)
Master (before capture edge) Tck / 4
Slave (after enable edge)
0
12
tRise
Rise time
Outputs: SCK,MOSI,MISO
(20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
13
tFall
Fall time
Outputs: SCK,MOSI,MISO
(70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
100
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
Note:
Measurement points are taken with reference to VIH-VIH / VOH-VOH for positive pulse and VIL-VIL / VOL-VOL for negative pulse
(1) Values guaranteed by design.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
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