Table 8. Detailed Register Map
Page
Block
(Decimal)
Core
N/A
I/O
Port
5:4,2:0
INT
0
WDT
I/O
2
Port
3
I/O
3
Port
5
7
SPI
11
STIM
Reg.
No.
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R224
R225
R226
R228
R229
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R252
R253
R254
R244
R245
R246
R240
R241
R242
R243
R240
R241
R242
R243
Register
Name
CICR
FLAGR
RP0
RP1
PPR
MODER
USPHR
USPLR
SSPHR
SSPLR
P0DR
P1DR
P2DR
P4DR
P5DR
EITR
EIPR
EIMR
EIPLR
EIVR
NICR
WDTHR
WDTLR
WDTPR
WDTCR
WCR
P3C0
P3C1
P3C2
P5C0
P5C1
P5C2
SPDR
SPCR
SPSR
SPPR
STH
STL
STP
STC
ST92141 - GENERAL DESCRIPTION
Description
Central Interrupt Control Register
Flag Register
Pointer 0 Register
Pointer 1 Register
Page Pointer Register
Mode Register
User Stack Pointer High Register
User Stack Pointer Low Register
System Stack Pointer High Reg.
System Stack Pointer Low Reg.
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 4 Data Register
Port 5 Data Register
External Interrupt Trigger Register
External Interrupt Pending Reg.
External Interrupt Mask-bit Reg.
External Interrupt Priority Level Reg.
External Interrupt Vector Register
Nested Interrupt Control
Watchdog Timer High Register
Watchdog Timer Low Register
Watchdog Timer Prescaler Reg.
Watchdog Timer Control Register
Wait Control Register
Port 3 Configuration Register 0
Port 3 Configuration Register 1
Port 3 Configuration Register 2
Port 5 Configuration Register 0
Port 5 Configuration Register 1
Port 5 Configuration Register 2
SPI Data Register
SPI Control Register
SPI Status Register
SPI Prescaler Register
Counter High Byte Register
Counter Low Byte Register
Standard Timer Prescaler Register
Standard Timer Control Register
Reset
Value
Hex.
87
00
xx
xx
xx
E0
xx
xx
xx
xx
FF
FF
FF
FF
FF
00
00
00
FF
x6
00
FF
FF
FF
12
7F
00
00
00
FF
00
00
00
00
00
00
FF
FF
FF
14
Doc.
Page
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26
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28
30
30
30
30
79
52
53
53
53
54
54
90
90
90
90
91
79
145
145
146
146
95
95
95
95
17/179
9