ST92T163N4D0 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92T163N4D0

8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT

STMicroelectronics 

ST92163 - ELECTRICAL CHARACTERISTICS

WATCHDOG TIMING TABLE

(VDD = 3.0 - 5.5V (1) , TA = 0°C + 70°C, CLoad = 50pF, fINTCLK = 24MHz, Push-pull output configuration,

unless otherwise specified)

N° Symbol

Parameter

1 TwWDOL WDOUT Low Pulse Width

2 TwWDOH WDOUT High Pulse Width

3 TwWDIL

4 TwWDIH

WDIN High Pulse Width

WDIN Low Pulse Width

Value (Note)

Formu la

Min

167

4 x (Psc+1) x (Cnt+1) x Tck

(Psc+1) x (Cnt+1) x TWDIN

333

with TWDIN ≥ 8 x Tck

167

4 x (Psc+1) x (Cnt+1) x Tck

(Psc+1) x (Cnt+1) x TWDIN

333

with TWDIN ≥ 8 x Tck

≥ 4 x Tck

167

≥ 4 x Tck

167

Unit

Max

ns

2.8

s

ns

ns

2.8

s

ns

ns

ns

Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,

watchdog prescaler and counter programmed values.

The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz, with minimum and

maximum prescaler value and minimum and maximum counter value.

(1) 3.0 - 4.0V voltage range is only available on devices with suffix L or V, with different frequency limitatio ns (L: 8 MHz, V: 16 MHz)

Legend:

Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;

2 x OSCIN period when OSCIN is divided by 2;

OSCIN period x PLL factor when the PLL is enabled.

Psc = Watchdog Prescaler Register content (WDTPR): from 0 to 255

Cnt = Watchdog Couter Registers content (WDTRH,WD TRL): from 0 to 65535

TWDIN = Watchdog Input signal period (WDIN)

WATCHDOG TIMING

214/224

Share Link: