PSD934210MT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD934210MT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Product Term Allocator

The CPLD has a Product Term Allocator. The PS-

Dabel compiler uses the Product Term Allocator to

borrow and place product terms from one macro-

cell to another. The following list summarizes how

product terms are allocated:

s McellAB0-McellAB7 all have three native

product terms and may borrow up to six more

s McellBC0-McellBC3 all have four native product

terms and may borrow up to five more

s McellBC4-McellBC7 all have four native product

terms and may borrow up to six more.

Each macrocell may only borrow product terms

from certain other macrocells. Product terms al-

ready in use by one macrocell are not available for

another macrocell.

If an equation requires more product terms than

are available to it, then “external” product terms

are required, which consume other Output Macro-

cells (OMC). If external product terms are used,

extra delay is added for the equation that required

the extra product terms.

This is called product term expansion. PSDsoft

Express performs this expansion as needed.

Loading and Reading the Output Macrocells

(OMC). The Output Macrocells (OMC) block oc-

cupies a memory location in the MCU address

space, as defined by the CSIOP block (see the

section entitled “I/O Ports”, on page 45). The flip-

flops in each of the 16 Output Macrocells (OMC)

can be loaded from the data bus by a MCU. Load-

ing the Output Macrocells (OMC) with data from

the MCU takes priority over internal functions. As

such, the preset, clear, and clock inputs to the flip-

flop can be overridden by the MCU. The ability to

load the flip-flops and read them back is useful in

such applications as loadable counters and shift

registers, mailboxes, and handshaking protocols.

Data can be loaded to the Output Macrocells

(OMC) on the trailing edge of Write Strobe (WR,

CNTL0) (edge loading) or during the time that

Write Strobe (WR, CNTL0) is active (level load-

ing). The method of loading is specified in PSDsoft

Express Configuration.

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