PSD934210MT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD934210MT
STMicroelectronics
PSD934210MT Datasheet PDF : 89 Pages
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PSD834F2V
Figure 19. Interfacing the PSD with an 80C31
RESET
RESET
80C31
31
EA/VP
19 X1
18 X2
9 RESET
12
13
INT0
14
15
INT1
T0
T1
1
2
3
4
5
6
P1.0
P1.1
P1.2
P1.3
P1.4
7
P1.5
P1.6
8 P1.7
39
P0.0
P0.1
38
37
P0.2
P0.3
P0.4
36
35
P0.5
P0.6
P0.7
34
33
32
P2.0 21
P2.1 22
P2.2 23
P2.3 24
P2.4 25
P2.5
P2.6
P2.7
26
27
28
17
RD
WR 16
PSEN 29
30
ALE/P
11
TXD
RXD 10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE
RESET
80C251. The Intel 80C251 MCU features a user-
configurable bus interface with four possible bus
configurations, as shown in Table 16.
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD7-AD0
PSD
30
31
32
33
34
ADIO0
ADIO1
ADIO2
ADIO3
35 ADIO4
36
37
ADIO5
ADIO6
ADIO7
39 ADIO8
40
41
42
ADIO9
ADIO10
ADIO11
43 ADIO12
44 ADIO13
45
46
ADIO14
ADIO15
47 CNTL0 (WR)
50 CNTL1(RD)
49 CNTL2 (PSEN)
10 PD0-ALE
9 PD1
8 PD2
48
RESET
AD[ 7:0]
PA0
29
28
PA1 27
PA2
PA3
25
24
PA4 23
PA5
PA6
PA7
22
21
PB0
7
6
PB1
PB2
5
PB3
PB4
4
3
2
PB5
PB6
52
PB7 51
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
20
19
18
17
14
13
12
11
AI02880C
Table 16. 80C251 Configurations
Configuration 80C251 Read/Write Pins
WR
1
RD
PSEN
2
WR
PSEN only
3
WR
PSEN only
WR
4
RD
PSEN
Connecting to PSD Pins
CNTL0
CNTL1
CNTL2
CNTL0
CNTL1
CNTL0
CNTL1
CNTL0
CNTL1
CNTL2
Page Mode
Non-Page Mode, 80C31
compatible A7-A0 multiplex with
D7-D0
Non-Page Mode
A7-A0 multiplex with D7-D0
Page Mode
A15-A8 multiplex with D7-D0
Page Mode
A15-A8 multiplex with D7-D0
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