SI3232 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3232

DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING

Silicon Laboratories 

Si3232

Table 10. Switching Characteristics—SPI

(VDD, VDD1–VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF)

Parameter

Symbol

Test

Conditions

Min

Typ

Max

Cycle Time SCLK

tc

Rise Time, SCLK

tr

Fall Time, SCLK

tf

Delay Time, SCLK Fall to SDO

td2

Transition

0.062

—

—

—

—

25

—

—

25

—

—

20

Delay Time, CS Rise to SDO Tristate

td3

Setup Time, CS to SCLK Rise

tsu1

Hold Time, SCLK Rise to CS Rise

th1

Setup Time, SDI to SCLK Rise

tsu2

Hold Time, SCLK Rise to SDI Rise

th2

SDI to SDITHRU Propagation Delay

—

—

20

15

—

—

20

—

—

25

—

—

20

—

—

—

6

—

Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VDD –0.4 V, VIL = 0.4 V

Unit

µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

tr

tr

tc

SCLK

CS

SDI

SDO

tsu1

th1

tsu2

th2

td2

td3

Figure 1. SPI Timing Diagram

Preliminary Rev. 0.96

13

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