SI3232 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3232

DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING

Silicon Laboratories 

Si3232

Table 11. Switching Characteristics—PCLK and FSYNC Timing

(VDD, VDD1–VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF)

Parameter

Symbol

Test

Conditions

Min 1

Typ 1

Max 1 Units

PCLK Period

tp

122

—

3706

Valid PCLK Inputs

—

256

—

—

512

—

—

768

—

—

1.024

—

—

1.536

—

—

1.544

—

—

2.048

—

—

4.096

—

—

8.192

—

FSYNC Period2

tfs

—

125

—

PCLK Duty Cycle Tolerance

tdty

40

50

60

PCLK Period Jitter Tolerance

tjitter

—

—

±120

Rise Time, PCLK

tr

—

—

25

Fall Time, PCLK

tf

—

—

25

Setup Time, FSYNC to PCLK Fall

tsu1

25

—

—

Hold Time, FSYNC to PCLK Fall

th1

20

—

—

FSYNC Pulse Width

twfs

tp/2

—

125 µs–tp

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4 V, VIL = 0.4 V.

2. FSYNC source is assumed to be 8 kHz under all operating conditions.

ns

kHz

kHz

kHz

MHz

MHz

MHz

MHz

MHz

MHz

µs

%

ns

ns

ns

ns

ns

ns

PCLK

tp

tr

tf

tsu1

FSYNC

th1

tfs

Figure 2. PCLK, FSYNC Timing Diagram

14

Preliminary Rev. 0.96

Share Link: