SI4010-C2-GS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI4010-C2-GS

CRYSTAL-LESS SOC RF TRANSMITTER

Silicon Laboratories 

Si4010-C2

34.1. Interrupt Flag Generation

Timer 2 has a single interrupt signal going to interrupt controller. Internally, there are 2 interrupt flags,

TMR2INTH for high half of the timer and TMR2INTL for low half of the timer, which are combined to gener-

ate the final interrupt signal. The low half has a local interrupt flag enable TMR2INTL_EN control bit.

TMR2INTH

TMR2INTL

TMR2INTL_EN

TMR2SPLIT

TMR2H_CAP

TMR2L_CAP

TMR2H_RUN

TMR2L_RUN

Interrupt

Figure 34.1. Timer Interrupt Generation

Setting of the interrupt flags depends on the width and functional modes of each timer or its half.

 Wide mode

l Timer mode

TMR2INTH set if TMR2H overflows

TMR2INTL set if TMR2L overflows

l Capture mode 

TMR2INTH set if capture event happens and TMR2H, TMR2L 16-bit value gets captured

TMR2INTL set if TMR2H overflows.

Note: This is an exception when low interrupt flag gets set based on the high half of the timer. This is a

supplemental information for the interrupt handler about the capture, indicating that the 16-bit counter overflew

in between captures.

 Split mode

l Timer mode

TMR2INTH set if TMR2H overflows

TMR2INTL set if TMR2L overflows

l Capture mode 

TMR2INTH set by capture event when TMR2H gets captured 

TMR2INTL set by capture event when TMR2L gets captured

Each of the modes is described in a separate section. There is a clock selection register TMR_CLKSEL

common for both Timer 2 and Timer 3.

132

Rev. 1.0

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