SI4010-C2-GS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI4010-C2-GS

CRYSTAL-LESS SOC RF TRANSMITTER

Silicon Laboratories 

TMR_CLKSEL

Si4010-C2

clk_sys

clk_sys/12

rtc_tick (5.33us)

rtc_pulse (100us)

2

0

1

2

3

TMR2H_RUN

2

0

1

2

3

TMR2L_RUN

TMR2H

TMR2RH

Reload

TMR2L

TMR2INTH

TMR2INTL

TMR2INTL_EN

TMR2SPLIT

TMR2H_CAP

TMR2L_CAP

TMR2H_RUN

TMR2L_RUN

Interrupt

TMR2RL

Reload

Figure 34.4. Two 8-bit Timers in Timer/Timer Configuration (Split Mode)

34.5. 8-Bit Capture/Capture Mode (Split Mode)

When TMR2SPLIT=1, TMR2L_CAP=1 and TMR2H_CAP=1, both halves operate independently in 8-bit

capture modes. However, the capture event is the same for both timers. The clock sources for each timer

are selected independently, so one timer can capture short pulses while the other one long pulses, for

example.

Each 8-bit timer is free running, counts up and overflows from 0xFF to 0x00. Each time a capture event is

received, the contents of the timer registers (TMR2H and TMR2L) are latched into the corresponding timer

reload registers (TMR2RH and TMR2RL). Common capture event INT0 (INT1 for Timer 3) sets both high

and low half interrupt flags TMR2INTH and TMR2INTL at the same time.

The capture event can also generate its own external interrupt on top of the timer interrupt, if enabled by

the application. If the capture timer is stopped (TMR2L_RUN=0), the capture event still captures the cur-

rent counter register TMR2L into the reload register TMR2RL and sets the flag TRM2INTL. Same indepen-

dently applies to the upper half TMR2H with its respective registers and flags.

Rev. 1.0

135

Share Link: