ST72334J/N, ST72314J/N, ST72124J
INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
FETCH NEXT INSTRUCTION
N
INTERRUPT
PENDING?
Y
N
EXECUTE INSTRUCTION
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt mapping
N°
Source
Block
Description
RESET Reset
TRAP
Software Interrupt
0
Not used
1
MCC/RTC Main Clock Controller Time Base Interrupt
CSS
or Clock Security System Interrupt
2
ei0
External Interrupt Port A3..0
3
ei1
External Interrupt Port F2..0
4
ei2
External Interrupt Port B3..0
5
ei3
External Interrupt Port B7..4
6
Not used
7
SPI
SPI Peripheral Interrupts
8
TIMER A TIMER A Peripheral Interrupts
9
TIMER B TIMER B Peripheral Interrupts
10
SCI
SCI Peripheral Interrupts
11 Data-EEPROM Data EEPROM Interrupt
12
Not used
13
Register
Label
N/A
MCCSR
CRSR
N/A
SPISR
TASR
TBSR
SCISR
EECSR
Priority
Order
Exit
from
HALT1)
Highest yes
Priority no
yes
no
Lowest
Priority
Address
Vector
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from
ACTIVE-HALT mode only.
34/153