ST72314J4B7(2003) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72314J4B7
(Rev.:2003)

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

STMicroelectronics 

ST72334J/N, ST72314J/N, ST72124J

POWER SAVING MODES (Cont’d)

11.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two low-

est power consumption modes of the MCU. They

are both entered by executing the ‘HALT’ instruc-

tion. The decision to enter either in ACTIVE-HALT

or HALT mode is given by the MCC/RTC interrupt

enable flag (OIE bit in MCCSR register).

MCCSR Power Saving Mode entered when HALT

OIE bit

instruction is executed

0 HALT mode

1 ACTIVE-HALT mode

11.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction when the OIE bit of the Main Clock Con-

troller Status register (MCCSR) is set (see Section

14.2 "MAIN CLOCK CONTROLLER WITH REAL

TIME CLOCK TIMER (MCC/RTC)" on page 52 for

more details on the MCCSR register).

The MCU can exit ACTIVE-HALT mode on recep-

tion of either an MCC/RTC interrupt, a specific in-

terrupt (see Table 5, “Interrupt mapping,” on

page 34) or a RESET. When exiting ACTIVE-

HALT mode by means of a RESET or an interrupt,

a 4096 CPU cycle delay occurs. After the start up

delay, the CPU resumes operation by servicing

the interrupt or by fetching the reset vector which

woke it up (see Figure 23).

When entering ACTIVE-HALT mode, the I bit in

the CC register is cleared to enable interrupts.

Therefore, if an interrupt is pending, the MCU

wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator

and its associated counter (MCC/RTC) are run-

ning to keep a wake-up time base. All other periph-

erals are not clocked except those which get their

clock supply from another clock generator (such

as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVE-

HALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering ACTIVE-HALT mode while the Watchdog

is active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

Figure 22. ACTIVE-HALT Timing Overview

ACTIVE 4096 CPU CYCLE

RUN HALT

DELAY

RUN

HALT

INSTRUCTION

[MCCSR.OIE=1]

RESET

OR

INTERRUPT

FETCH

VECTOR

Figure 23. ACTIVE-HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=1)

OSCILLATOR ON

PERIPHERALS 1) OFF

CPU

OFF

I BIT

0

N

RESET

N

Y

INTERRUPT 2)

Y

OSCILLATOR ON

PERIPHERALS 1) OFF

CPU

ON

I BIT

X 3)

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR ON

PERIPHERALS ON

CPU

ON

I BITS

X 3)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. Peripheral clocked with an external clock source

can still be active.

2. Only the MCC/RTC interrupt and some specific

interrupts can exit the MCU from ACTIVE-HALT

mode (such as external interrupt). Refer to

Table 5, “Interrupt mapping,” on page 34 for more

details.

3. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is

set during the interrupt routine and cleared when

the CC register is popped.

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