ST72314J4B7(2003) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72314J4B7
(Rev.:2003)

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

STMicroelectronics 

ST72334J/N, ST72314J/N, ST72124J

POWER SAVING MODES (Cont’d)

11.4.2 HALT MODE

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

‘HALT’ instruction when the OIE bit of the Main

Clock Controller Status register (MCCSR) is

cleared (see Section 14.2 "MAIN CLOCK CON-

TROLLER WITH REAL TIME CLOCK TIMER

(MCC/RTC)" on page 52 for more details on the

MCCSR register).

The MCU can exit HALT mode on reception of ei-

ther a specific interrupt (see Table 5, “Interrupt

mapping,” on page 34) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,

the oscillator is immediately turned on and the

4096 CPU cycle delay is used to stabilize the os-

cillator. After the start up delay, the CPU resumes

operation by servicing the interrupt or by fetching

the reset vector which woke it up (see Figure 25).

When entering HALT mode, the I bit in the CC reg-

ister is forced to 0 to enable interrupts. Therefore,

if an interrupt is pending, the MCU wakes immedi-

ately.

In HALT mode, the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” op-

tion bit of the option byte. The HALT instruction

when executed while the Watchdog system is en-

abled, can generate a Watchdog RESET (see

Section 18.1 on page 144 for more details).

Figure 24. HALT Timing Overview

4096 CPU CYCLE

RUN HALT

DELAY

RUN

HALT

INSTRUCTION

[MCCSR.OIE=0]

RESET

OR

INTERRUPT

FETCH

VECTOR

Figure 25. HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=0)

ENABLE

WATCHDOG

WDGHALT 1)

0

DISABLE

1

WATCHDOG

RESET

OSCILLATOR OFF

PERIPHERALS 2) OFF

CPU

OFF

I BIT

0

N

RESET

N

Y

INTERRUPT 3)

Y

OSCILLATOR ON

PERIPHERALS OFF

CPU

ON

I BIT

X 4)

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR ON

PERIPHERALS ON

CPU

ON

I BITS

X 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source

can still be active.

3. Only some specific interrupts can exit the MCU

from HALT mode (such as external interrupt). Re-

fer to Table 5, “Interrupt mapping,” on page 34 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is

set during the interrupt routine and cleared when

the CC register is popped.

38/153

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