PIC16C717/770/771
After the A/D module has been configured as desired
and the analog input channels have their correspond-
ing TRIS bits selected for port inputs, the selected
channel must be acquired before conversion is
started. The A/D conversion cycle can be initiated by
setting the GO/DONE bit. The A/D conversion begins
and lasts for 13TAD. The following steps should be fol-
lowed for performing an A/D conversion:
1. Configure port pins:
• Configure analog input mode (ANSEL)
• Configure pin as input (TRISA or TRISB)
2. Configure the A/D module
• Configure A/D Result Format / voltage refer-
ence (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
3. Configure A/D interrupt (if required)
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
FIGURE 11-3: A/D BLOCK DIAGRAM
4. Wait the required acquisition time (3TAD)
5. Start conversion
• Set GO/DONE bit (ADCON0)
6. Wait 13TAD until A/D conversion is complete, by
either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
7. Read A/D Result registers (ADRESH and
ADRESL), clear ADIF if required.
8. For next conversion, go to step 1, step 2 or step
3 as required.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRESH and
ADRESL registers will be updated with the partially
completed A/D conversion value. That is, the ADRESH
and ADRESL registers will contain the value of the
current incomplete conversion.
Note:
Do not set the ADON bit and the GO/
DONE bit in the same instruction. Doing so
will cause the GO/DONE bit to be automat-
ically cleared.
CHS<3:0>
VAIN
(Input voltage)
VREF+
(Reference
voltage +)
AVDD
VRH
VRL
RB1/AN5/SS
RB0/AN4/INT
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
RA0/AN0
A/D
Converter
VCFG<2:0>
VREF-
(Reference
voltage -)
AVSS
VCFG<2:0>
VRL
© 1999 Microchip Technology Inc.
Advanced Information
DS41120A-page 117