PIC16C717-I/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16C717-I/SS Datasheet PDF : 200 Pages
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PIC16C717/770/771
12.3 Reset
The PIC16C717/770/771 devices have several differ-
ent resets. These resets are grouped into two classifi-
cations; power-up and non-power-up. The power-up
type resets are the power-on and brown-out resets
which assume the device VDD was below its normal
operating range for the device’s configuration. The non-
power up type resets assume normal operating limits
were maintained before/during and after the reset.
• Power-on Reset (POR)
• Programmable Brown-out Reset (PBOR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (during normal operation)
Some registers are not affected in any reset condition.
Their status is unknown on a power-up reset and
unchanged in any other reset. Most other registers are
placed into an initialized state upon reset, however they
are not affected by a WDT reset during sleep, because
this is considered a WDT Wakeup, which is viewed as
the resumption of normal operation.
Several status bits have been provided to indicate
which reset occurred (see Table 12-4). See Table 12-6
for a full description of reset states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 12-5.
These devices have a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 12-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT Time-out
Module
VDD rise Power-on Reset
detect
VDD
Programmable
Brown-out BODEN
OSC1
OST/PWRT
OST
10-bit Ripple counter
PWRT
Dedicated
Oscillator
10-bit Ripple counter
S
Chip_Reset
R
Q
Enable PWRT
Enable OST
© 1999 Microchip Technology Inc.
Advanced Information
DS41120A-page 129
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