INDEX
A
A/D .................................................................................... 113
A/D Converter Enable (ADIE Bit) ................................ 19
ADCON0 Register..................................................... 113
ADCON1 Register............................................. 113, 115
ADRES Register ....................................................... 113
Block Diagram........................................................... 117
Configuring Analog Port............................................ 116
Conversion time ........................................................ 123
Conversions .............................................................. 119
converter characteristics ................... 169, 170, 171, 174
Faster Conversion - Lower Resolution Tradeoff ....... 123
Internal Sampling Switch (Rss) Impedence .............. 121
Operation During Sleep ............................................ 124
Sampling Requirements............................................ 121
Sampling Time .......................................................... 121
Source Impedance.................................................... 121
Special Event Trigger (CCP)....................................... 57
A/D Conversion Clock ....................................................... 118
ACK..................................................................................... 78
Acknowledge Data bit, AKD ................................................ 70
Acknowledge Pulse............................................................. 78
Acknowledge Sequence Enable bit, AKE ........................... 70
Acknowledge Status bit, AKS ............................................. 70
ACKSTAT ........................................................................... 92
ADCON0 Register............................................................. 113
ADCON1 Register..................................................... 113, 115
ADRES.............................................................................. 113
ADRES Register ........................................... 13, 14, 113, 124
AKD..................................................................................... 70
AKE ..................................................................................... 70
AKS ..................................................................................... 70
Application Note AN578, "Use of the SSP Module in the I2C
Multi-Master Environment."................................................. 77
Architecture
PIC16C717/PIC16C717 Block Diagram ....................... 5
PIC16C770/771/PIC16C770/771 Block Diagram ......... 6
Assembler
MPASM Assembler................................................... 149
B
Banking, Data Memory ................................................. 11, 16
Baud Rate Generator .......................................................... 86
BF ..................................................................... 68, 78, 92, 95
Block Diagrams
Baud Rate Generator.................................................. 86
I2C Master Mode......................................................... 84
I2C Module .................................................................. 77
RA3:RA0 and RA5 Port Pins .................... 28, 30, 31, 37
SSP (I2C Mode) .......................................................... 77
SSP (SPI Mode).......................................................... 71
BOR. See Brown-out Reset
BRG .................................................................................... 86
Brown-out Reset (BOR) .................................... 125, 131, 132
Buffer Full bit, BF ................................................................ 78
Buffer Full Status bit, BF ..................................................... 68
Bus Arbitration .................................................................. 103
Bus Collision Section ........................................................ 103
Bus Collision During a RESTART Condition..................... 106
Bus Collision During a Start Condition .............................. 104
Bus Collision During a Stop Condition .............................. 107
PIC16C717/770/771
C
Capture (CCP Module) ....................................................... 56
Block Diagram ............................................................ 56
CCP Pin Configuration ............................................... 56
CCPR1H:CCPR1L Registers ..................................... 56
Changing Between Capture Prescalers ..................... 56
Software Interrupt ....................................................... 56
Timer1 Mode Selection............................................... 56
CCP1CON .......................................................................... 15
CCP2CON .......................................................................... 15
CCPR1H Register......................................................... 13, 15
CCPR1L Register ............................................................... 15
CCPR2H Register............................................................... 15
CCPR2L Register ............................................................... 15
CKE .................................................................................... 68
CKP .................................................................................... 69
Clock Polarity Select bit, CKP............................................. 69
Code Examples
Loading the SSPBUF register .................................... 72
Code Protection ........................................................ 125, 139
Compare (CCP Module) ..................................................... 56
Block Diagram ............................................................ 57
CCP Pin Configuration ............................................... 56
CCPR1H:CCPR1L Registers ..................................... 56
Software Interrupt ....................................................... 56
Special Event Trigger ........................................... 51, 57
Timer1 Mode Selection............................................... 56
Configuration Bits ............................................................. 125
D
D/A...................................................................................... 68
Data Memory ...................................................................... 11
Bank Select (RP<1:0> Bits).................................. 11, 16
General Purpose Registers ........................................ 11
Register File Map ....................................................... 12
Special Function Registers......................................... 13
Data/Address bit, D/A ......................................................... 68
DC Characteristics
PIC16C717/770/771 ................................................. 158
Development Support ....................................................... 149
Device Differences............................................................ 189
Direct Addressing ............................................................... 25
E
Enhanced Capture/Compare/PWM (CCP)
CCP1
CCPR1H Register .............................................. 55
CCPR1L Register ............................................... 55
Enable (CCP1IE Bit)........................................... 19
Timer Resources ........................................................ 56
Enhanced Capture/Compare/PWM (ECCP)....................... 55
External Power-on Reset Circuit....................................... 130
F
Firmware Instructions ....................................................... 141
Flowcharts
Acknowledge .............................................................. 99
Master Receiver ......................................................... 96
Master Transmit.......................................................... 93
Restart Condition........................................................ 90
Start Condition............................................................ 88
Stop Condition .......................................................... 101
FSR Register .......................................................... 13, 14, 15
© 1999 Microchip Technology Inc.
Advanced Information
DS41120A-page 191