ST10F280 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F280 Datasheet PDF : 186 Pages
| |||
ST10F280
Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable system reaction similar to a
standard interrupt service (branching to a
dedicated vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag
register (TFR). Except when another higher
prioritized trap service is in progress, a hardware
trap will interrupt any other program execution.
Hardware trap services cannot not be interrupted
by standard interrupt or by PEC interrupts.
information of the associated source, which is
required during one round of prioritization, the
upper 8 bit of the respective register are reserved.
All interrupt control registers are bit-addressable
and all bit can be read or written via software.
This allows each interrupt source to be
programmed or modified with just one instruction.
When accessing interrupt control registers
through instructions which operate on Word data
types, their upper 8 bit (15...8) will return zeros,
when read, and will discard written data.
8.3 - Interrupt Control Registers
All interrupt control registers are identically
organized. The lower 8 bit of an interrupt control
register contain the complete interrupt status
The layout of the Interrupt Control registers shown
below applies to each xxIC register, where xx
stands for the mnemonic for the respective
source.
xxIC (yyyyh / zzh)
SFR Area
Reset Value: - - 00h
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
- xxIR xxIE
RW RW
ILVL
RW
GLVL
RW
Bit
GLVL
ILVL
xxIE
xxIR
Function
Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
52/186
Share Link: 