ST10F280 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST10F280

16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM

STMicroelectronics 

ST10F280

8.4 - Exception and Error Traps List

Table 8 shows all of the possible exceptions or error conditions that can arise during run-time :

Table 8 : Exceptions or Error Conditions that Can Arise During Run-time

Exception Condition

Trap Flag

Trap

Vector

Vector Location

Trap Number

Trap *

Priority

Reset Functions

MAXIMUM

Hardware Reset

RESET

00’0000h

00h

III

Software Reset

RESET

00’0000h

00h

III

Watchdog Timer Overflow

RESET

00’0000h

00h

III

Class A Hardware Traps

Non-Maskable Interrupt

NMI NMITRAP

00’0008h

02h

II

Stack Overflow

STKOF STOTRAP

00’0010h

04h

II

Stack Underflow

STKUF STUTRAP

00’0018h

06h

II

Class B Hardware Traps

Undefined Opcode

UNDOPC BTRAP

00’0028h

0Ah

I

Protected Instruction Fault PRTFLT BTRAP

00’0028h

0Ah

I

Illegal Word Operand Access ILLOPA BTRAP

00’0028h

0Ah

I

Illegal Instruction Access

ILLINA BTRAP

00’0028h

0Ah

I

Illegal External Bus Access ILLBUS BTRAP

00’0028h

0Ah

I

MAC Trap

MACTRP BTRAP

00’0028h

0Ah

I

MINIMUM

Reserved

[2Ch –3Ch]

[0Bh – 0Fh]

Software Traps

TRAP Instruction

Any [00’0000h– 00’01FCh] Any [00h – 7Fh] Current

in steps of 4h

CPU Priority

* - All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets.

- Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level.

- The resets have the highest priority level and the same trap number.

- The PSW.ILVL CPU priority is forced to the highest level (15) when these exeptions are serviced.

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