ST10R272 View Datasheet(PDF) - STMicroelectronics
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ST10R272 Datasheet PDF : 77 Pages
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ST10R272L - INTERRUPT AND TRAP FUNCTIONS
6.2 Hardware Traps
Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware
traps cause immediate non-maskable system reaction similar to a standard interrupt service
(branching to a dedicated vector table location). The occurrence of a hardware trap is
additionally signified by an individual bit in the trap flag register (TFR). Except when another
higher prioritized trap service is in progress, a hardware trap will interrupt any actual program
execution. In turn, hardware trap services can not normally be interrupted by standard or PEC
interrupts. The following table shows all of the possible exceptions or error conditions that can
arise during run-time:
Exception Condition
Trap Flag
Trap Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
NMI
Stack Overflow
STKOF
Stack Underflow
STKUF
Class B Hardware Traps:
Undefined opcode
UNDOPC
Protected instruction fault PRTFLT
Illegal word operand access ILLOPA
Illegal instruction access ILLINA
Illegal external bus access ILLBUS
MAC trap
MACTRP
Reserved
Software Traps
TRAP Instruction
RESET
00’0000h
00h
III
RESET
00’0000h
00h
III
RESET
00’0000h
00h
III
NMITRAP 00’0008h
02h
II
STOTRAP 00’0010h
04h
II
STUTRAP 00’0018h
06h
II
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
[2Ch – 3Ch]
0Ah
I
0Ah
I
0Ah
I
0Ah
I
0Ah
I
0Ah
I
[0Bh – 0Fh]
Any [00’0000h Any
Current
– 00’01FCh] [00h – 7Fh] CPU
steps of 4h
Priority
Table 6 Exceptions or error conditions
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