ST10R272 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10R272 Datasheet PDF : 77 Pages
| |||
ST10R272L - ELECTRICAL CHARACTERISTICS
Parameter
Data hold after RdCS
Data float after RdCS
(with RW-delay)1 2
Data float after RdCS
(no RW-delay)1 2
Address hold after
RdCS, WrCS
Data hold after WrCS
Symbol
Max CPU Clock 50MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
t51 SR 0
t53 SR –
t68 SR –
t55 CC -5 + tF
–
0
13 + tF + –
2
2tA
3
+
tF+
2
2tA
–
–
-5 + tF
–
ns
2TCL - 7
ns
+
tF
+
2
2tA
TCL - 7
ns
+
tF
+
2
2tA
–
ns
t57 CC 3 + tF
–
TCL - 7 + tF –
ns
Table 18 Demultiplexed bus
1) Output loading is specified using Figure 13 with CL = 5 pF.
2) This delay assumes that the following bus cycle is a demultiplexed bus cycle and that the
data bus will only be driven externally when the RD or RdCs signal becomes active. RW-
delay and tA refer to the following bus cycle. If the following bus cycle is a muxtiplexed bus
cycle, refer to equivalent multiplexed AC timing (which are still applicable due to automatic
insertion an idle state (2TCL) when switching from Demultiplexed to Multiplexed Bus Mode.
61/77
1
Share Link: 