ST10R272 View Datasheet(PDF) - STMicroelectronics
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ST10R272 Datasheet PDF : 77 Pages
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ST10R272L - ELECTRICAL CHARACTERISTICS
16.3.5 CLKOUT and READY/READY
VDD = 3.3 V ± 0.3 V
VSS = 0 V
TA = -40 to +85 °C
CL = 50 pF
Parameter
Max. CPU Clock
Symbol = 50 MHz
min.
max.
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
CLKOUT cycle time
t29 CC 20
CLKOUT high time
t30 CC 5
CLKOUT low time
t31 CC 5
CLKOUT rise time1)
t32 CC –
CLKOUT fall time1
t33 CC –
CLKOUT rising edge to
ALE falling edge
t34 CC -3 + tA
Synchronous READY
setup time to CLKOUT
t35 SR 9
Synchronous READY
hold time after CLKOUT
t36 SR 0
Asynchronous READY
low time
t37 SR 27
Asynchronous READY
setup time2)
t58 SR 9
Asynchronous READY
hold time2
t59 SR 0
Async. READY hold time t60 SR 0
after RD, WR high (Demulti-
plexed Bus)3)2
20
–
–
31
31
5 + tA
–
–
–
–
2TCL
TCL – 5
TCL – 5
–
–
-3 + tA
9
0
2TCL + 7
9
–
0
0
0
+ 2tA+ tc+ tF 3
2TCL
ns
–
ns
–
ns
31
ns
31
ns
5 + tA
ns
–
ns
–
ns
–
ns
–
ns
–
ns
TCL - 10
ns
+ 2tA+ tc+ tF3
Table 19 CLKOUT and READY/READY
1) Measured between 0.3 and 2.7 volts
2) These timings assure recognition at a specific clock edge for test purposes only.
3) Demultiplexed bus is the worst case. For multiplexed bus, 2TCL should be added
to the maximum values. This adds even more time for deactivating READY.
2tA and tC refer to the following bus cycle, tF refers to the current bus cycle.
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