ST10R272L - ELECTRICAL CHARACTERISTICS
6 Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional
MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this
delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is
zero.
7 The next external bus cycle may start here.
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