ST62P32BQ3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST62P32BQ3

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART

STMicroelectronics 

ST62T32B ST62E32B

INSTRUCTION SET (Cont’d)

Arithmetic and Logic. These instructions are

used to perform the arithmetic calculations and

logic operations. In AND, ADD, CP, SUB instruc-

tions one operand is always the accumulator while

the other can be either a data space memory con-

tent or an immediate value in relation with the ad-

dressing mode. In CLR, DEC, INC instructions the

operand can be any of the 256 data space ad-

dresses. In COM, RLC, SLA the operand is always

the accumulator.

Table 22. Arithmetic & Logic Instructions

Instruction

Addressing Mode

Bytes

ADD A, (X)

Indirect

1

ADD A, (Y)

Indirect

1

ADD A, rr

Direct

2

ADDI A, #N

Immediate

2

AND A, (X)

Indirect

1

AND A, (Y)

Indirect

1

AND A, rr

Direct

2

ANDI A, #N

Immediate

2

CLR A

Short Direct

2

CLR r

Direct

3

COM A

Inherent

1

CP A, (X)

Indirect

1

CP A, (Y)

Indirect

1

CP A, rr

Direct

2

CPI A, #N

Immediate

2

DEC X

Short Direct

1

DEC Y

Short Direct

1

DEC V

Short Direct

1

DEC W

Short Direct

1

DEC A

Direct

2

DEC rr

Direct

2

DEC (X)

Indirect

1

DEC (Y)

Indirect

1

INC X

Short Direct

1

INC Y

Short Direct

1

INC V

Short Direct

1

INC W

Short Direct

1

INC A

Direct

2

INC rr

Direct

2

INC (X)

Indirect

1

INC (Y)

Indirect

1

RLC A

Inherent

1

SLA A

Inherent

2

SUB A, (X)

Indirect

1

SUB A, (Y)

Indirect

1

SUB A, rr

Direct

2

SUBI A, #N

Immediate

2

Notes:

X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected

# . Immediate data (stored in ROM memory)* . Not Affected

rr. Data space register

Cycles

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

4

Flags

Z

C

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

*

*

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

*

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

∆

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