ST72260G, ST72262G, ST72264G
13.12 10-BIT ADC CHARACTERISTICS
TA = -40°C to 85°C, unless otherwise specified
Symbol
Parameter
Conditions
fADC
VAIN
CADC
tCONV
ADC clock frequency
Conversion voltage range
Internal sample and hold capacitor
Conversion time
fADC=4MHz
RAIN
CAIN
fAIN
External input impedance
External capacitor on analog input
Variation frequency of analog input
signal
Min
0.41)
VSS
Typ
6
28
112
Max
4
VDD
see
Figure
105 and
Figure
1062)3)4)
Unit
MHz
V
pF
µs
1/fADC
kΩ
pF
Hz
Figure 105. RAIN max. vs fADC with CAIN=0pF3)
Figure 106. Recommended CAIN/RAIN values4)
45
40
35
30
25
20
15
10
5
0
0
4 MHz
2 MHz
1 MHz
10
30
70
CPARASITIC (pF)
1000
100
10
1
0.1
0.01
Cain 10 nF
Cain 22 nF
Cain 47 nF
0.1
1
10
fAIN(KHz)
Figure 107. Analog Input equivalent circuit
VDD
ST72XXX
VAIN
RAIN
AINx
CAIN
VT
0.6V
2kΩ(max) 10-Bit A/D
Conversion
VT
0.6V
IL
±1µA
CADC
6pF
Notes:
1. Data based on design simulation.
2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
3. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
4. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.
152/171