ST7MC2N6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7MC2N6

8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™

STMicroelectronics 

ST7MC1xx/ST7MC2xx

MOTOR CONTROLLER (Cont’d)

CONTROL REGISTER B (MCRB)

Read/Write

Reset Value: 0000 0000 (00h)

7

6

5

4

3

2

1

0

0 CPB* HDM* SDM* OCV OS2* OS1 OS0

Bit 7= Reserved, must be kept at reset value.

Bit 6= CPB*: Compare Bit for Zero-crossing detec-

tion.

0: Zero crossing detection on falling edge

1: Zero crossing detection on rising edge

Bit 5= HDM*: Hardware Demagnetization event

Mask bit

0: Hardware Demagnetization disabled

1: Hardware Demagnetization enabled

Bit 4= SDM*: Simulated Demagnetization event

Mask bit

0: Simulated Demagnetization disabled

1: Simulated Demagnetization enabled

Bit 3 = OCV: Over Current Handling in Voltage

mode

0: Over Current protection is OFF

1:Over current protection is ON

This bit acts as follows

Table 60. Over current handling

CLIM bit CLI bit OCV bit Output effect Interrupt

0

0

x

Normal running

mode

No

0

1

x

PWM is put off as

Current loop effect

No

1

0

x

Normal running

mode

No

1

1

0

PWM is put off as

Current loop effect

Yes

All MCOx outputs

1

1

1

are put in reset

Yes

state (MOE reset) 1)

Note 1: This feature is also available when using

the three PWM outputs (PCN bit=1 in the MDTG

register), providing that the VOC1bit = 0 (MCRA

register). See section 10.6.8.2 on page 186

Bits 2:0 = OS2*, OS[1:0]: Operating output mode

Selection bits

Refer to the Step behaviour diagrams (Figure 109,

Figure 110) and Table 61, “Step Behaviour/ sen-

sorless mode,” on page 212.

These bits are used to define the various PWM

output configurations.

Note: OS2 is the only preload bit.

Table 61. Step Behaviour/ sensorless mode

OS2

bit

PWM after

C and

before D

OS1

bit

0

0

On High

Channels

1

0

1

On Low

Channels

1

PWM after

D and

before Z

On High

Channels

On Low

Channels

On High

Channels

On Low

Channels

PWM after

OS0

Z and

before next

C

0

On high

channels

1

On low

channels

0

On high

channels

1

On low

channels

0

On high

channels

1

On low

channels

0

On high

channels

1

On low

channels

Note: For more details, see Step behaviour dia-

grams (Figure 109 and Figure 110).

* Preload bits, new value taken into account at the

next C event. A C event is generated at each write

to MPHST in Direct Access mode.

212/309

1

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