ST7MC2N6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7MC2N6
STMicroelectronics
ST7MC2N6 Datasheet PDF : 309 Pages
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Bits 2:0 = VR[2:0]: BEMF/demagnetisation Refer-
ence threshold
These bits select the Vref value as shown in the
Table 64. The Vref value is used for BEMF and
Demagnetisation detection.
Table 64. Threshold voltage setting
VR2 VR1 VR0 Vref voltage threshold
1
1
1
Threshold voltage set by ex-
ternal MCVREF pin
1
1
0
3.5V*
1
0
1
2.5V*
1
0
0
2V*
0
1
1
1.5V*
0
1
0
1V*
0
0
1
0.6V*
0
0
0
0.2V*
*Typical values for VDD=5V
PHASE STATE REGISTER (MPHST)
Read/Write
Reset Value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
IS1* IS0* OO5* OO4* OO3* OO2* OO1* OO0*
Bit 7:6 = IS[1:0]*: Input Selection bits
These bits mainly select the input to connect to
comparator as shown in Table 65. The fourth con-
figuration (IS[1:0] = 11) specifies that an incremen-
tal encoder is used (in that case MCIA and MCIB
digital signals are directly connected to the incre-
mental encoder interface and the analog multi-
plexer is bypassed.
Table 65. Input Channel Selection
IS1 IS0
Channel selected
0
0
MCIA
0
1
MCIB
1
0
MCIC
1
1 Both MCIA and MCIB: Encoder Mode
Bits 5:0 =OO[5:0]*: Channel On/Off bits
These bits are used to switch channels on/off at
the next C event if the DAC bit =0 or directly if
DAC=1
0: Channel Off, the relevant switch is OFF, no
PWM possible
1: Channel On the relevant switch is ON, PWM is
possible (not signifiant when PCN or DTE bit is
set).
Table 66. OO[5:0] Bit Meaning
OO[5:0]
0
1
Output Channel State
Inactive
Active
* Preload bits, new value taken into account at
next C event.
Caution: As the MPHST register contains bits with
preload, the whole register has to be written at
once. This means that a Bit Set or Bit Reset in-
struction on only one bit without preload will have
the effect of resetting all the bits with preload.
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