ST92195C/D View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92195C/D

48-96 Kbyte ROM HCMOS MCU WITH ON-SCREEN DISPLAY AND TELETEXT DATA SLICER

STMicroelectronics 

ST92195C/D - TIMING AND CLOCK CONTROLLER

FREQUENCY MULTIPLIERS (Cont’d)

For the Off-chip filter components please refer to

the Required External Components figure provid-

ed in the first section of the data sheet.

The frequency multipliers are off during and upon

exiting from the reset phase. The user must pro-

gram the desired multiplying factor, start the multi-

plier and then wait for its stability (refer to the Elec-

trical Charateristics chapter for the specified de-

lay).

Once the Core/Peripherals multiplier is stabilized,

the Main Clock controller can be re-programmed

(through the FMSL bit, MCCR.6) to provide the fi-

nal frequency (INTCLK) to the CPU.

The frequency multipliers are automatically

switched off when the µP enters in HALT mode

(the HALT mode forces the control register to its

reset status).

Table 12. Examples of CPU speed choice

Crystal

Frequency

4 MHz

4 MHz

4 MHz

FML

(3:0)

4

5

6

Internal Frequency

(Fimf)

10 MHz

12 MHz

14 MHz

4 MHz

7

4 MHz

8

4 MHz

11

16 MHz

18 MHz

24 MHz

Note: 24 MHz is the max. CPU authorized frequency.

Table 13. DOTCK/2 frequency choices

SKW

(3:0)

DOTCK/2

8

18 MHz

9

20 MHz(*)

10

22 MHz

11

(*) Preferred values for 4/3.

24 MHz (**)

(**) 16/9 screen formats.

Note: 18 MHz is the min. DOTCK/2 authorized frequency.

Table 14. Data Slicer over-sampling clock

(other values are not allowed)

Crystal

Frequ.

4 MHz

8 MHz

Prescale

factor

64

128

Multiply

factor

777

777

7x Text

Frequency (Fslic)

48.5625 MHz

48.5625 MHz

Table 15. External PLL Filter Stabilisation time

Clock Pin Name

MCFM

PXFM

TXCF

Clock Name

Main Clock PLL Filter Input Pin

Pixel Clock PLL Filter Input Pin

Teletext PLL Clock Filter input Pin

Control Register

MCCR

PXCCR

SLCCR

Stabilization Period

35 ms.

35 ms

200 ms

65/249

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