ST92195C/D View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92195C/D
STMicroelectronics
ST92195C/D Datasheet PDF : 249 Pages
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ST92195C/D - TIMING AND CLOCK CONTROLLER
REGISTER DESCRIPTION (Cont’d)
PLL CLOCK CONTROL REGISTER (PXCCR)
R251 - Read/Write
Register Page: 39
Reset value: 0000 0000 (00h)
Bit 6= SLDIV2. Divide-by-2 Prescaler.
0: No division, 4 MHz crystal is used
1: Divide-by-2 prescaler enabled. To be used with
an 8 MHz crystal.
7
6
5
4
3
2
1
0
PXCE 0
0
0
0
0
0
0
Bit 7= PXCE. Pixel Clock Enable bit.
0: Pixel and TDSRAM interface clocks are blocked
1: Pixel clock is sent to the display controller and
TDSRAM interface.
Bits 6:0= These bits are reserved.
SLICER CLOCK CONTROL
(SLCCR)
R252 - Read/ Write
Register Page: 39
Reset value: 0000 0000 (00h)
REGISTER
7
6
5
4
32
10
SLIEN SLDIV2 0 VMOD 0 0 0 0
The HALT mode forces the register to its initializa-
tion state.
Bit 7= SLIEN. Frequency Multiplier Enable bit.
0: FM disabled (reset state), low-power consump-
tion mode.
1: FM is enabled, providing clock to the Teletext
Data Slicer.
Note: This PLL clock is fed to the VPS/WSS data
slicer if the VW_EN bit of the VPSWSSCR register
is set.
Bit 5= This bit is reserved.
Bit 4= VMOD: Video mode selection.
This bit is used to allow a correct teletext slicing
depending on the selected video mode (50Hz or
60Hz). It is set and cleared by software.
0: 50 Hz. (41 bytes stored per TV line)
1: 60 Hz (bit rate at 5.733 MHz. and 33 bytes
stored per TV line).
Bits 3:0= These bits are reserved.
5.2.1 Register Mapping
The Timing Controller has 4 dedicated registers,
mapped in a ST9+ register file page (the page ad-
dress is 39 (27h)), as follows :
Page 39 (27h)
FEh Skew Corrector Control Register
FDh
Main Clock Control Register
FCh
SLicer Clock Control Register
FBh
Pixel Clock Control Register
SKCCR
MCCR
SLCCR
PXCCR
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