STA32813TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STA32813TR

2.1-channel high-efficiency digital audio system

STMicroelectronics 

Register description

STA328

Table 9. Register summary

Address Name

D7

D6

D5

D4

D3

D2

D1

D0

0x1E

A1cf2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9

C3B8

0x1F

A1cf3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1

C3B0

0x20

0x21

A2cf1

A2cf2

C4B23

C4B15

C4B22

C4B14

C4B21

C4B13

C4B20

C4B12

C4B19

C4B11

C4B18

C4B10

C4B17

C4B9

C4B16

C4B8

0x22

A2cf3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1

C4B0

0x23

B0cf1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

0x24

B0cf2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9

C5B8

0x25

0x26

B0cf3

Cfud

C5B7 C5B6 C5B5 C5B4 C5B3

Reserved Reserved Reserved Reserved RA

C5B2

R1

C5B1

WA

C5B0

W1

0x27

MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

0x28

MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

0x29

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0x2A

0x2B

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

0x2C

FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

0x2D

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

6.1

Configuration register A (addr 0x00)

D7

D6

D5

D4

FDRB

TWAB

TWRB

IR1

0

1

1

0

D3

D2

D1

D0

IR0

MCS2

MCS1

MCS0

0

0

1

1

Table 10. Master clock select

Bit R/W RST Name

Description

0

RW 1

MCS0

Master clock select: Selects the ratio between the input

I2S sample frequency and the input clock.

1

RW 1

MCS1

2

RW 0

MCS2

The STA328 will support sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz.

Therefore the internal clock will be:

" 32.768 MHz for 32 kHz

" 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

" 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample

frequency (fs). The correlation between the input clock and the input sample rate is

determined by the status of the MCSx bits and the IR (input rate) register bits. The MCSx

20/57

Share Link: