Register description
STA335BWS
6.15
Fault detect recovery constant registers (addr 0x2B to 0x2C)
FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the
TRISTATE output is immediately asserted low and held low for the time period specified by
this constant. A constant value of 0x0001 in this register is ~0.083 ms. The default value of
0x000C specifies ~0.1 ms.
D7
FDRC15
0
D7
FDRC7
0
D6
FDRC14
0
D6
FDRC6
0
D5
FDRC13
0
D5
FDRC5
0
D4
FDRC12
0
D4
FDRC4
0
D3
FDRC11
0
D3
FDRC3
1
D2
FDRC10
0
D2
FDRC2
1
D1
FDRC9
0
D1
FDRC1
0
D0
FDRC8
0
D0
FDRC0
0
6.16
Device status register (addr 0x2D)
D7
PLLUL
D6
FAULT
D5
UVFAULT
D4
OVFAULT
D3
OCFAULT
D2
OCWARN
D1
TFAULT
D0
TWARN
This read-only register provides fault and thermal-warning status information from the power
control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault
or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.
" PLLUL: 0 = PLL locked, 1 = PLL not locked.
" FAULT: 0 = fault detected on power bridge, 1 = normal operation
" UVFAULT: 0 = VCCxX internally detected < undervoltage threshold.
" OVFAULT: 0 = VCCxX internally detected > overvoltage threshold.
" OCFAULT: 0 = overcurrent fault detected
" OCWARN: 0 = overcurrent warning.
" TFAULT: 0 = thermal fault. Junction temperature over limit detection.
" TWARN: 0 = thermal warning. The junction temperature is close to the fault condition.
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