STA335BWS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA335BWS Datasheet PDF : 68 Pages
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STA335BWS
Register description
6.17 EQ coefficients and DRC configuration register (addr 0x31)
D7
XOB
0
D6
D5
Reserved
0
0
D4
AMGC[3]
0
Table 32. SEL bitfield description
SEL[1,0]
00/11
01
10
Bank 0 activated
Bank 1 activated
Bank 2 activated
D3
AMGC[2]
0
D2
reserved
0
D1
SEL1
0
EQ RAM bank selected
D0
SEL0
0
Table 33. AMGC bitfield description
AMGC[3,2]
Anti-clipping and DRC preset selected
00
01
10/11
DRC/Anti-clipping (default)
DRC/Anti-clipping
Reserved, do not use
AC0, AC1, AC2 settings are designed for loudspeaker protection function, limiting at the
minimum any audio artefact introduced by typical anti-clipping/DRC algorithms. More
detailed information can be retrieved in the “Configurable output power rate using
STA335BW” and “STA335BWS vs STA335BW” application notes.
Table 34. AMGC bitfield description
AMGC[1:0]
Mode
00
AC0, stereo anti-clipping 0dB limiter
01
AC1, stereo anti-clipping +1.25dB limiter
10
AC2, stereo anti-clipping +2dB limiter
11
reserved do not use
Bit XOB can be used to bypass the crossover filters. Logic 1 means that the function is not
active. In this case, high pass crossover filter works as a pass through on the data path
(b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have
zero signal on channel 3 data processing (all the coefficients are at logic 0).
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