STA335BWS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STA335BWS Datasheet PDF : 68 Pages
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Application
7
Application
STA335BWS
7.1
Application schematic and power supplies
Figure 17 shows a circuit diagram of a typical application for STA335BWS. Particular care
has to be given to the layout of the PCB, especially the power supplies. The 3.3 Ω resistors
on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This
helps to prevent unwanted oscillation on the digital portion of the device due to inductive
tracks of the PCB. This same rule is also be applied to all the decoupling capacitors in order
to limit any kind of spikes on all the supplies.
Figure 17. Application schematic
1000uF 35V
1uF 35V
100nF
100nF
1uF 35V
100nF
OUT2B
OUT2A
VCC
OUT1B
OUT1A
100nF
DDX3B
DDX3A
1 GND_SUB
2 SA
3 TEST_MODE
4 VSS
5 VCC_REG
6 OUT2B
7 GND2
8 VCC2
9 OUT2A
10 OUT1B
11 VCC1
12 GND1
13 OUT1A
14 GND_REG
15 VDD
16 CONFIG
17 DDX3B
18 DDX3A
VDD_DIG 36
GND_DIG 35
SCL 34
SDA 33
INT_LINE 32
RESET 31
SDI 30
LRCKI 29
BICKI 28
XTI 27
PLL_GND 26
FILTER_PLL 25
VDD_PLL 24
PWRDN 23
GND_DIG 22
VDD_DIG 21
TWARN/4A 20
EAPD/4B 19
3R3
3V3
100nF
3V3
SCL
SDA
INTL
GND_DIG
10K
DATA
LRCKI
BICKI
XTI
RESET
1nF
RESET
GND_DIG
BEAD
PLL_FILT
100nF
BEAD
PLL_GND
GND_DIG
3V3
PWDN
3R3
TW
EAPD
100nF
GND_DIG
3V3
7.2
PLL filter schematic
It is recommended to use the below scheme and values for the PLL loop filter to achieve the
best performances from the device in general application. Please be noted that the ground
of this filter scheme has to be connected to the ground of the PLL without any resistive path.
Concerning the component values, please take into account that the greater is the filter
bandwidth, the less is the lock time but the higher is the PLL output jitter.
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