STLC5412 View Datasheet(PDF) - STMicroelectronics
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Manufacturer
STLC5412 Datasheet PDF : 74 Pages
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STLC5412
Table 2: 2B1Q Encoding of 2B+ D Fields.
Data
Bit Pair
Quat # (relative)
# Bits
# Quats
Time →
b11b12
q1
BI
b13 b14 b15 b16
q2
q3
8
4
b17 b18
q4
b21b22
q5
W here:
b11 = first bit of B1 octet as received at the S/T interface
b18 = last bit of BI octet as received at the S/T interface
b21 = first bit of B2 octet as received at the S/T interface
b28 = last bit of B2 octet as received at the S/T interface
d1 d2 = consecutive D-channel bits (d1 is first bit of pair as received at the S/T interface)
qi = ith quat relative to start of given 18-bit 2B+D data field.
NOTE: There are 12 2B+D 18-bit fields per 1.5 msec basic frame.
Bg
b23 b24 b25 b26
q6
q7
8
4
b27 b28
q8
D
d1d2
q9
2
1
Table 3: Network-to-NT 2B1Q Superframe Technique and Overhead Bit Assignments.
FRAMING 2B+D
Quat Positions
Bit Positions
1-9
1-18
10-117
19-234
118s
235
118m
236
Overhead Bits (M1-M6)
119s
237
119m
238
120s
239
120m
240
Super
Frame
#
A
B,C,...
Basic
Frame
#
1
2
3
4
5
6
7
8
Sync
2B+D
M1
M2
M3
M4
M5
M6
Word
ISW
2B+D
eoca1
eoca2
eoca3
act
1
1
SW
2B+D
eocdm
eoci1
eoci2
dea
1
febe
SW
2B+D
eoci3
eoci4
eoci5
1
crc1
crc2
SW
2B+D
eoci6
eoci7
eoci8
1
crc3
crc4
SW
2B+D
eoca1
eoca2
eoca3
1
crc5
crc6
SW
2B+D
eocdm
eoci1
eoci2
1
crc7
crc8
SW
2B+D
eoci3
eoci4
eoci5
uoa
crc9
crc10
SW
2B+D
eoci6
eoci7
eoci8
aib
crc11
crc12
NT-to-Network superframe delay offset from Network-to-NT superframe by 60 ± 2 quats (about 0.75
ms). All bits than the Sync Word are scrambled.
Symbols & Abbreviations:
”1” reserve = reserved bit for future standard; set = 1
eoc embedded operations channel
a = address bit
dm = data/message indicator
i = information (data/message)
SW synchronization word
ISW inverted synchronization word
s sign bit (first) in quat
m magnitude bit (second) in quat
act activation bit
crc cyclic redundancy check: covers 2B+D & M4
1 = most significant bit
2 = next most significant bit
etc
febe far end block error bit (set = 0 for errored
superframe)
dea deactivation bit (set = 0 to announce deactivation)
uoa u only activation bit (set = 1 to activate S/T)
aib alarm indication bit (set = 0 to indicate interruption)
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