STLC5412 View Datasheet(PDF) - STMicroelectronics
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Description
Manufacturer
STLC5412 Datasheet PDF : 74 Pages
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STLC5412
Table 4: NT-to-Network 2B1Q Superframe Technique and Overhead Bit Assignments.
FRAMING 2B+D
Quat Positions
1-9
10-117
118s
Overhead Bits (M1-M6)
118m 119s 119m 120s
120m
Bit Positions
1-18
19-234 235
236
237
238
239
240
Super
Basic
Frame
Frame
#
1
2,3,...
#
Sync Word 2B+D
M1
M2
M3
M4
M5
M6
1
ISW
2B+D
eoca1
eoca2
eoca3
act
1
1
2
SW
2B+D eocdm
eoci1
eoci2
ps1
1
febe
3
SW
2B+D
eoci3
eoci4
eoci5
ps2
crc1
crc2
4
SW
2B+D
eoci6
eoci7
eoci8
ntm
crc3
crc4
5
SW
2B+D
eoca1
eoca2
eoca3
cso
crc5
crc6
6
SW
2B+D eocdm
eoci1
eoci2
1
crc7
crc8
7
SW
2B+D
eoci3
eoci4
eoci5
sai
crc9
crc10
8
SW
2B+D
eoci6
eoci7
eoci8
1
crc11
crc12
NT-to-Network superframe delay offset from Network-to-NT superframe by 60 ± 2 quats (about 0.75 ms).
All bits than the Sync Word are scrambled.
Symbols & Abbreviations:
”1” reserve = reserved bit for future standard; set = 1
eoc embedded operations channel
a = address bit
dm = data/message indicator
i = information (data/message)
SW synchronization word
ISW inverted synchronization word
s sign bit (first) in quat
m magnitude bit (second) in quat
act activation bit
ps1, power status bits (set = 0 to indicate power
ps2 problems)
ntm NT in Test Mode bit (set = 0 to indicate test mode
cso cold-start-only bit (set = 1 to indicate cold-start-only
crc cyclic redundancy check: covers 2B+D & M4
1 = most significant bit
2 = next most significant bit
etc
febe far end block error bit (set = 0 for errored
superframe)
sai S/T interface activation indication bit.
Figure 6: Example of 2B1Q Quaternary Symbols.
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