STLC5412 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5412 Datasheet PDF : 74 Pages
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STLC5412
When Block error counter reachs this value, an
Interrupt relative to BEC2 register is loaded in the
interrupt stack. This can be used as an early
alarm in case of degraded transmission.
Receive status Register - read command
(RXOH) (Write only)
EOC M4 M56 ACT 0 STATUS 0 RST
Reset to zero of all the RXOH bits is automatic.
EOC Receive EOC status register read.
When EOC bit is set to one, UID automatically
loads the current value of RXEOC register in the
interrupt stack independently of any status
change.
M4 Receive M4 overhead bits status register
read.
When M4 bit is set to one, UID automatically
loads the current value of RXM4 register in the in-
terrupt stack independently of any status change.
M56 Receive M5 and M6 overhead bits status
register read.
When M56 bit is set to one, UID automatically
loads the current value of RXM56 register in the
interrupt stack independently of any status
change.
ACT Activation indication status.
When ACT bit is set to one, UID automatically
loads the current value of RXACT register in the
interrupt stack independently of any status
change.
In GCI mode, the RXACT read back always uses
the monitor channel.
STATUS
When STATUS bit is set to one, UID automat-
ically loads the current value of STATUS register
in the interrupt stack independently of any status
change.
RST RESET (MICROWIRE/DSI configuration
only).
When RST bit is set to one, UID is fully reset in-
cluding configuration registers, state machine and
all coefficients and reset to their default value.
UID enters in the power-down state.
Transmit EOC register (TXEOC)
After reset: FFFH
XEOC1 XEOC2 XEOC3 XEOC4 XEOC5 XEOC6 XEOC7 XEOC8
50/74
TXEOC Register is constituted of 12 bits, 3 bits
address (EFG), 1 bit data/message Flag (H), 8
bits information (XEOC1 - XEOC8). When trans-
mitting SL2/SL3 or SN3 signal. STLC5412 shall
continuously send into the EOC channel field the
eoc bits twice per superframe. TXEOC register is
loaded in the transmit register at each half a su-
perframe.
The address of this register is composed only of 4
bits. Read-back can be performed by means of a
read-back command 6100H.
Dect Mode Eoc Register (DECTEOC)
After reset: FFFH
DEOC1 DEOC2 DEOC3 DEOC4 DEOC5 DEOC6 DEOC7 DEOC8
12 bits register to store the DECT EOC message,
3 bits address (EFG), 1 bit data/message Flag
(H), 8 bits information (DEOC1 - DEOC8) This
register is significant only in DECT mode. In LT
DECT mode the byte is transmitted 3 times in the
EOC channel starting from the superframe identi-
fied by the DECSYNC pulse on the SFSx pin.
Once the DECTEOC byte has been transmitted 3
times, the content of the EOC channel returns to
the previous existing value. In NT DECT mode if
the received EOC message field is detected 3
times identical to the DECTEOC register, the de-
vice generates a pulse on the pin SFSx synchro-
nous with the SFSr pulse. Read back can be per-
formed by means of command B100H.
Receive EOC register (RXEOC)
(read only)
After reset: FFFH
REOC1 REOC2 REOC3 REOC4 REOC5 REOC6 REOC7 REOC8
The RX EOC Register is constituted of 12 bits.
When the line is fully activated (super frame syn-
chronized) and when a new eoc message is re-
ceived and validated in accordance with the crite-
ria selected in the Configuration Register OPR,
the RX EOC Register is queued in the interrupt
register stack. The address of this register is com-
posed only of 4 bits.
It is always possible to read this register by writ-
ing EOC = 1 in RXOH register
Identification Register (IDR)
Fixed value: CCCC 00001000
(read only 12 bit register)
When a read-back operation of IDR register is en-
tered, UID loads the Identification Register in the
interrupt stack. This register provides a reserved
identification code agreed by GCI standard:
CCCC 00001000
IDR register is accessible via two addresses (See
page 34).
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