STLC5432 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5432

2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

STMicroelectronics 

STLC5432

RDS0/1Receive Data Select Bit 0/1

When the PRS analyser is validated

SAV = 1 (TCR2), Sequence is checked by

the analyser during the Time Slot(s)

selected by TCR2.

RDS1

0

0

1

1

RDS0

0

1

0

1

Sou rce

Sequence comes from

Memory input.

Sequence comes from

memory Output.

Sequence comes from

Data Input (DIN pin). Instead

of sequence, ”1” are

transmitted onto the line.

Sequence comes from Data

Input (DIN pin). Sequence is

transmitted onto the line.

ALS

AISX

ASP

data stream coming from the decoder

HDB3-BIN, just before frame memory input.

Alarm Line Signal to be transmitted.

When this bit is at 1, AIS or APS are

transmitted onto the line.

Alarm Indication signal.

If ALS is at ”1”, and AISX is at ”1”:

Alarm Indication signal (All 1s) is transmit-

ted onto the line.

If ALS is at ”1” and AISX is at ’0”:

Auxiliary pattern (0-1-0-1-0-1...) is transmit-

ted onto the line.

Alternate Single Pulse

If ASP = 1 The L01 andL02 outputsdeliver

pulse every 3.9 microseconds. On theline,

onewill bepositive,the next negativeand so on.

When the PRS generator is validated,

9.26 CR4 Configuration Register 4

SGV = 1 (TCR1 register), Sequence is

transmitted by the generator during the Time 7

0

Slot(s) selected by TCR1.

1 EQV AVT DEL DCP M2 M1 M0

RDS1

0

1

RDS0

X

X

Destination

Sequence is transmitted

onto the line. Loopback 1

or 3 can be validated.

Sequence is transmitted on

Data Out (DOUT pin).

DOHZ DOUT High Impedance

DOHZ = 1, DOUT pin is high impedance

DOHZ = 0, DOUT pin is in accordance with

TS0E bit of CR5 register.

After Reset = 80H

The first three bits of this register, M 0/2, must not

be changed by the microprocessor if the serial µP

is selected, they can be programmed only in par-

allel interface mode. If Serial interface or Stand

Alone mode is chosen, then Multiplexes are at 2

048kb/s and local clock frequency may be either

2 048 kHz or 4 096 kHz.

NB : If parallel micro interface is selected, DOUT

will be valid after writing CR4 Register.

9.25 CR3 Configuration Register 3

M 0/2

7

0

1 ASP Nu AISX ALS LP3 LP2 LP1

After Reset = 80H

LP1 Loop Back 1

This loop back is the nearestto the line side

pins. If LP1 = 1 incoming data are replaced by

outgoing data.

If AISX=0, loopback is transparent(outgoing

data is transmitted)

If AISX=1, Alarm IndicationSignal is transmitted. DCP

LP2 Loop Back 2

Loopback located between the HDB3/BIN

decoderoutput and the BIN/HDB3 encoder

input. Loop back 2 is always transparent.

If LP2 = 1 Data received from the line are

returned to the line.

LP3 Loop Back 3

Multiplex DIN and Multiplex DOUT

M2 = 1

Multiplexes are at 8 192 kb/s. Each

multiplex includes 128 Time Slots.

M0 and M1 indicate the Time Slots

selected by the device.

M2 = 0 and M1 = 1

Multiplexes are at 4 096 kb/s. Each

multiplex includes 64 Time Slots.

M0 indicates the Time Slots selected

by the device.

M2 = M1 = 0

Multiplexes are at 2 048 kb/s. Each

multiplex includes 32 Time Slots.

Double Clock Pulse

When this bit is at ”1”, local clock frequency

value is twice the data rate value.

Data In are shifted on the second falling

edge of the local clock (LCLK).

When this bit is at ”0”, local clock frequency

and data rate value have same value.

Data in are shifted on the falling edge of the

local clock.

If LP3 = 1 Frames and Multiframes genera- DEL Delayed mode.

ted by the emitter are connected instead of

21/46

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