STLC5432 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5432

2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

STMicroelectronics 

STLC5432

9.34 TCR3 Test Configuration Register 3

7

0

1 CRCC EBC PELC PULS FASC ODTS TWI

After Reset = 80H

TWI TSO corrupted TWICE.

If FASC=1 and TWI=1, Time Slot 0 selected

by ODTS is corrupted twice only.

If FASC=1 and TWI=0, Time Slot 0 selected

by ODTS is corrupted three times only.

ODTS Odd Time Slot 0

If FASC=1 and ODTS=1, Odd Time Slot

zero is transmitted with Bit 2 at ”0”.

If FASC=1 and ODTS=0, Even Time Slot

Zero is transmitted with Bit 2 at ”1”.

FASC

Frame Alignment Signal Corrupted.

In accordance with ODTS and TWI.

If FASC=1, Time Slot 0 transmitted is corrupted.

After transmitting twice or three times

consecutively,FASC changes from ”1” to ”0”.

PULS PULSE

First case : SGV = 0 (TCR2 Register)

If PELC=1 and PULS=1, 512 consecutive

pulses are transmitted on the line during

frame 0 and frame 1. If PELC=1 and

PULS=0, no pulses are transmitted during

16 time-bit (7,8 microseconds).

Second case : SGV = 1 (TCR2 Register)

PULSE is ignored; if PELC changes ”0” to

”1”, one pseudo random sequence bit

transmitted is corrupted.After transmitting

corruptedbit, PELC changes”1” to ”0”.

PELC Pulses transmitted on the line are corupted

in accordance with PULS and SGV (TCR2

Register). After transmitting once time,

PELC changes from ”1” to ”0”.

EBC

E Bit Corrupted.

If EBC=1, E bit of the next frame 13 and E

bit of the next frame 15 will be transmitted

at ”0”. After transmitting once time, EBC

changes from ”1” to ”0”.

CRCC CRC4 corrupted

When CRCC is at ”1”, CRC4 transmitted

into multiframe is continuously corrupted.

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