STLC5432 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5432

2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

STMicroelectronics 

STLC5432

Figure 5: Main Alarm Processing

LINE STATE

RECEIVING

ALARMS

DETECTED

ALARMS

TRANSMITTED

ODD TS0

or

BIT 3

Ax

LOS

AIS

915

LOF

AR

WER

REGISTERS

(TSOXR)

AE Bit

ALR

CAR1

ALARMS

COMPLEM.

and

MERA

(CR1)

REGISTER

ALARM

REGISTER

Bit 0

Bit 1

Bit 2

Bit 3

Bit 5

D93TL050B

Bit 0

Figure 6: DIN and DOUT During Time slot 0.

Serial Interface

P0 + P1 = 0

During

Time Slot 0:

SA pin: 0V

Parallel Interface: P0 + P1 # 0

IF TSOE = 0 (CR5)

During Time Slot 0:

Dout pin is High Z.

IF TSOE = 1

During Time Slot 0:

Dout pin delivers consecutively:

Dout pin

delivers

messages

and

Din pin

receives

messages

ODD SKIP SLC Sa4R Sa5R Sa6R Sa7R Sa8R

ODD = 1 The contents of 31 Time Slots is related to

odd frame received from the line.

ODD = 0 The contents of 31 Time Slots is related to

even frame received from the line. (See Figure 6a).

Din pin receives eight bits:

SA pin: 5V

Stand Alone

During Time Slot 0:

Dout pin delivers eight alarms

SLC SKIP AR MFNR LOF B

Din pin is ignored during Time Slot 0

AIS LOS

X

X

X Sa4E Sa5E Sa6E Sa7E Sa8E

D93TL051E

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