Figure 16: Transmitter Side Timing
SIG = 0 DATA RATE AT 2048Kb/s
488ns
LCLK
(CLOCK)
tpd
BXDO
(DATA)
BXDI
(DATA)
tH
ts
SIG = 1 DATA RATE AT 64Kb/s
15.6µs
BXDO
(CLOCK)
BXDI
(DATA)
tH
ts
Figure 16a: Transmitter Side: Delay on BXD0 pin
D93TL062B
STLC5432
LFSX
LCLK
Example applied to DIN pin with Data Rate at 2048Kb/s
DIN
BIT 254
BIT 255
BIT 0
BIT 1
BIT 2
BXDO
BIT 253
BIT 254
BXDO output has 2 LCLK pulse of delay from DIN input
BIT 255
BIT 0
BIT 1
D96TL254
37/46