STLC5432 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5432

2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

STMicroelectronics 

STLC5432

Figure 20: Single Clock Delayed Mode.

LCLK

tH

LFSX

LFSR

BIT n

T

ts

tpd

DOUT

tH

ts

DIN

DCP = 0

DEL = 0

DEL = 1

Figure 21: Multiplex Diagram

SINGLE PULSE

T = 488ns MULTIPLEX AT 2Mb/s

T = 244ns MULTIPLEX AT 4Mb/s

T = 122ns MULTIPLEX AT 8Mb/s

NOT DELAYED MODE

BIT n IS THE FIRST BIT OF THE FRAME (125µs)

BIT 0 TIME SLOT ZERO (LIKE GCI)

DELAYED MODE

BIT n IS THE LAST BIT OF THE FRAME (125µs)

tpdz

D93TL066A

LCLK

DOUT 0

DOUT 1

DOUT 2

DOUT 3

3.9µs

EX: FOUR ST5432 OUTPUTS WHEN CONNECTED TO THE SAME MULTIPLEX AT 8Mb/s

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D93TL067

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