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STM32F050G4U7 View Datasheet(PDF) - STMicroelectronics

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STM32F050G4U7 Datasheet PDF : 97 Pages
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Electrical characteristics
STM32F050xx
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not
affect the ADC accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
Figure 24. ADC accuracy characteristics
4095
4094
4093
7
6
5
4
3
2
1
1
LSBIDEAL

VDDA

(2)
ET
(3)
EO
EL
ED
1 LSBIDEAL
EG
(1)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
0
1 2345 67
VSSA
4093 4094 4095 4096
VDDA
-36
Figure 25. Typical connection diagram using the ADC
RAIN(1)
AINx
VAIN
Cparasitic
6$$!
VT
0.6 V
VT
0.6 V
IL±1 μA
Sample and hold ADC
converter
RADC
12-bit
converter
CADC
-36
1. Refer to Table 49: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
74/97
Doc ID 023683 Rev 1

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