TDA1566TH View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

TDA1566TH

I²C-bus controlled dual channel 46 W/2Ω, single channel 92 W/1Ωamplifier with load diagnostic features

NXP Semiconductors. 

NXP Semiconductors

TDA1566

I2C-bus controlled dual channel/single channel amplifier

6.4.2 Instruction bytes

If R/W bit = 0, the TDA1566 expects 3 instruction bytes; IB1, IB2 and IB3. After a

power-on reset, all instruction bits are set to zero. In 1 Ω mode the instruction bits of

channel 1 are used. The instruction bits labelled ‘reserved for test’ should be set to zero.

Table 18. Instruction bytes

Bit Instruction byte IB1

D7

0 slow start enable

1 slow start disable

D6

0 channel 1 no clip

detect on DIAG

1 channel 1 clip detect

on DIAG

D5

0 channel 2 no clip

detect on DIAG

1 channel 2 clip detect

on DIAG

D4

0 no temperature pre-

warning on DIAG

1 temperature pre-

warning on DIAG

D3

reserved for test

D2

0 AC load detection

disabled; detection

slope counter reset

1 AC load detection

enabled

D1

0 DC load detection

disabled

1 DC load detection

enabled

D0

0 TDA1566 in standby

1 TDA1566 in mute or

operating (see

IB2[D0])

Instruction byte IB2

0 clip detect level on

3%

1 clip detect level on

7%

reserved for test

Instruction byte IB3

reserved for test

0 channel 1 26 dB gain

1 channel 1 16 dB gain

reserved for test

0 channel 2 26 dB gain

1 channel 2 16 dB gain

0 speaker protection or 0

short on DIAG

1 no speaker protection 1

or short on DIAG

reserved for test

0

1

0 slow mute (20 ms) 0

temperature pre-

warning on 145 °C

temperature pre-

warning on 122 °C

channel 1 enabled

channel 1 disabled

channel 2 enabled

1 fast mute (0.1 ms) 1 channel 2 disabled

0 offset fault on DIAG 0 balanced input

1 no set fault on DIAG 1 unbalanced input

0 channel 1 and

reserved for test

channel 2 operating

1 channel 1 and

channel 2 muted

6.4.3 Data bytes

If R/W = 1, the TDA1566 will send 3 data bytes to the microprocessor: DB1, DB2, and

DB3. All short diagnostic and offset detect bits are latched. All bits are reset after a read

operation except DB1[D7], DB2[D7], DB1[D4], DB2[D4], DB1[D5] and DB2[D5]. DB1[D2]

and DB2[D2] are set after a read operation, see Section 6.3.5. DB1[D7] and DB2[D7] are

reset when IB1[D2] is LOW. In 1 Ω mode the diagnostic information will be shown in DB1.

The content of the bits ‘reserved for test’ should be ignored.

TDA1566_2

Product data sheet

Rev. 02 — 20 August 2007

© NXP B.V. 2007. All rights reserved.

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