TDA7500ATR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TDA7500ATR Datasheet PDF : 41 Pages
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TDA7500A
Debug Port Interface
No.
Characteristics
1
DBCK rise time
2
DBCK fall time
3
DBCK Low
4
DBCK High
5
DBCK Cycle Time
6
DBRQN Asserted to DBOUT (ACK) Asserted
7
DBCK High to DBOUT Valid
8
DBCK High to DBOUT Invalid
9
DBIN Valid to DBCK Low (Set-up)
10
DBCK Low to DBIN Invalid (Hold)
DBOUT (ACK) Asserted to First DBCK High
DBOUT (ACK) Assertion Width
11
Last DBCK Low of Read Register to First DBCK High of
Next Command
12
Last DBCK Low to DBOUT Invalid (Hold)
DBSEL setup to DBCK
Figure 7. Debug Port Serial Clock Timing.
dclk = 40MHz
Unit
Min.
Max.
--
3
ns
--
3
ns
40
--
ns
40
--
ns
200
--
ns
5 TDSP
--
ns
--
42
ns
3
--
ns
15
--
ns
3
--
ns
2 Tc
--
ns
4.5 TDSP - 3 5 TDSP + 7
ns
7 TDSP + 10
--
ns
3
TDSP
--
ns
ns
Figure 8. Debug Port Acknowledge Timing.
22/40
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