TDA7500ATR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TDA7500ATR

DIGITAL AM/FM SIGNAL PROCESSOR

STMicroelectronics 

TDA7500A

s I2C and SPI interface

s XCHG Interface for DSP to DSP communication

s External Memory Interface (DRAM/SRAM) for time-delay and traffic information

s Double Debug Port

DATA AND PROGRAM MEMORY

Both DSP0 and DSP1 have Data and Program memories attached to them. Each of the memories are described

below and it is implied that there are two of each type, one set connected to DSP0 and the other to DSP1. The

only exception is the case of the P-RAM where DSP1 has a 2048 x 24-Bit PRAM and DSP0 has a 5.5K x 24-

Bit PRAM.

1024 x 24-Bit X-RAM (XRAM)

This is a 1024 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0)

is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be writ-

ten to and read from the Data ALU of the DSP core. The XDBx Bus is also connected to the Internal Bus Switch

so that it can be routed to and from all peripheral blocks.

1024 x 24 Bit Y-RAM (YRAM)

This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is gener-

ated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from

the Data ALU of the DSP core. The YDBx Bus is also connected to the Internal Bus Switch so that it can be

routed to and from other blocks.

2048 x 24-Bit Program RAM (PRAM 5.5K x 24-bit for DSP0)

This is a 2048 x 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit PRAM Ad-

dress, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching,

and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PRAM Data (Pro-

gram Code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the

PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding.

512 x 24-Bit Bootstrap ROM (PROM 256 x 24 Bit for DSP1)

This is a 512 x 24-Bit factory programmed Boot ROM used for storing the program sequence and for initializing

the DSP. Essentially this consists of reading the data via I2C, SPI or EMI interface and store it in PRAM, XRAM,

YRAM, and/or external DRAM.

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