Configuration Byte 1
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
RD1
RD0
P1.7 P3.7/RD# PSEN#
WR#
External
Memory
Read signal for all Write signal for all
0
0
A17 A16
external memory external memory
256 KB
locations
locations
Read signal for all Write signal for all
0
1
I/O pin A16
external memory external memory
128 KB
locations
locations
Read signal for all Write signal for all
1
0
I/O pin I/O pin
external memory external memory
64 KB
locations
locations
1
1
I/O pin
Read
signal for
regions 00:
and 01:
Read signal for
regions FE: and FF:
Write signal for all
external memory
locations
2 × 64 KB(1)
Notes: 1. This selection provides compatibility with the standard 80C51 hardware which has
separate external memory spaces for data and code.
20 AT/TSC8x251G2D
4135F–8051–11/06