Z8932320FEC View Datasheet(PDF) - Zilog
Part Name
Description
Manufacturer
Z8932320FEC Datasheet PDF : 61 Pages
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TIMER/COUNTERS
PRELIMINARY
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
The Z89323/373/393 has two 16-bit Timer/Counters that
can be independently configured to operate in various
modes. Each is implemented as a 16-bit Load Register
(TMLR) and a 16-bit down counter (TMR). Timer/Counter
inputs can be selected from among UI0 or UI1 pins and
outputs from among UO0 or UO1 pins. The Timer/Counter
clock is a scaled version of system clock. Each counter has
an 8-bit clock prescaler with divide count controlled by the
16-bit Prescaler Load Register (TPLR). The clock rates of
the two timer/counters are independent of each other.
External input events occur optionally on the rising edge,
the falling edge, or both rising and falling edges of the
input. Output actions on external pins can be programmed
to occur with either polarity. The Timer/Counter operational
modes are selected through the 16-bit Control Register
(TCTL). This register defines the operational modes of its
companion Timer (Figure 14).
Each Timer contains a set of five 16-bit Registers. The Ext
Register Assignment specifies the location of each Timer
Registers. All accesses to Timer Registers occur with zero
Wait States.
15
14 13 12 11 8 7 6 5 4
32 1 0
Test
MODE
OUT
INV
OUT
SEL
INP
EVENT
INP
SEL
CE
Count Enable
Input Select
Input Event
Output Select
Output Invert
Timer Mode
Reserved
Test Mode
Figure 14. TCTL Register
DS95DSP0101 Q4/95
23
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