Z8932320FEC View Datasheet(PDF) - Zilog
Part Name
Description
Manufacturer
Z8932320FEC Datasheet PDF : 61 Pages
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PRELIMINARY
TIMER/COUNTERS (Continued)
Z89323/373/393
16-BIT DIGITAL SIGNAL PROCESSORS
Timer Load Register (TMLR)
This 16-bit Register holds a value that is reloaded into timer
upon timer under flow.
15
0
Timer Reload Value
Timer Register (TMR)
TMR is a 16-bit down counter that holds the current Timer/
Counter value. It can be read as any ordinary register.
However, writing to TMR is different than writing to an
ordinary register. A write to TMR Register causes the
contents of TMLR Register to be written into it, causing the
Timer to be retriggered. Any data on DSP’s Memory Data
(MD) Bus is ignored during a write to TMR.
Timer Prescaler Load Register (TPLR)
The 16-bit TPLR Register holds the prescaler reload value
in its lower 8 bits. Bit 15 is the Timer's Interrupt Pending bit.
When set, it signifies an interrupt event in its companion
timer. The IP bit can only be set by the Timer. It can be
cleared only by software when it writes a value to this
register with a "1" in bit position 15; a "0" in bit position 15
will have no effect on the state of IP bit. Bits [14:8] must
always be written with 0s for future compatibility.
15 14
87
0
Test Zeros
Prescaler
Reload Value
15
0
Timer Register
Timer Prescale Register (TPR)
TPR is an 8-bit down counter that holds the current Prescaler
count value. It can be read as any ordinary register.
However, writing to TPR is different than writing to an
ordinary register. A write to TPR Register causes the lower
8-bit contents of TPLR Register to be written into it, causing
the Prescaler to be retriggered. Any data on DSP’s Memory
Data (MD) Bus is ignored during a write to TPR.
7
0
TPR
8-Bit Counter
26
DS95DSP0101 Q4/95
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